The present invention relates to accessing a test condition, and in particular to a method of conditionally executing computer instructions, a computer system and a computer program product.
Computer systems are known where execution of an instruction is predicated on some value identified or addressed in the instruction. According to one proposal, a multibit test code is defined in each instruction, the multibit test code indicating a certain test condition. That condition is checked against a condition code held in the computer system and set by an earlier instruction. If the condition defined in the test code is satisfied by the condition code, the instruction is executed. If it is not, then the instruction is not executed.
In that arrangement, the number of test conditions which can be identified is restricted by the available length of the address field addressing the test register in the instruction. More test conditions can be defined, but at the expense of using up more bits in the instruction.
According to one aspect of the present invention there is provided a method of executing computer instructions each of which define first and second operands and an operation to be carried out on said operands, each instruction containing an address field of a predetermined bit length which identifies a test register holding a plurality of test bits greater than said predetermined bit length, the method comprising: accessing said first and second source operands; accessing the test register identified in the address field and deriving from that test register a test code defining a test condition; checking the test condition against at least one condition code; and selectively carrying out the operation defined in the instruction in dependence on whether the condition code satisfies the test condition.
Some instructions operate on so-called packed operands, each of which contain a plurality of packed objects in respective lanes. In that case, the method can comprise checking the test condition against a condition code set for each lane of the operand and carrying out the operation only in those lanes for which the condition code satisfies the test condition.
The test register can contain a condition code selector wherein the method comprises checking the test condition against the condition code selected by the condition code selector in the addressed test register and selectively carrying out the operation in dependence on whether the condition code satisfies the test condition.
In the described embodiment, the address field in the instruction is 3 bits long, and the test register contains 8 bits, a 4 bit test code, a 3 bit condition code selector and a single side field bit. The side field bit is used in computer systems which have first and second execution channels with corresponding first and second associated sets of condition codes. The side field bit denotes which set of condition codes is to be accessed. It is possible to arrange the computer system such that an instruction executed on one of the execution channels updates its associated set of condition codes which is then accessible by an instruction executing on the other execution channel.
The invention further provides a computer system for conditionally carrying out an operation defined in a computer instruction, the computer system comprising: fetch and decoding circuitry for fetching and decoding a sequence of instructions from a program memory; at least one execution unit for conditionally executing said instructions and including means for accessing a test register defined in an address field of the instruction; a condition code register for holding a set of condition codes used in determining whether or not the instruction is to be executed; and a test register holding a test code defining a test condition to be checked against at least one condition code in the set of condition codes to determine whether or not the instruction is to be executed.
The invention further provides a computer program product comprising program code means in the form of a sequence of computer instructions each of which define first and second operands and an operation to be carried out on said operands, each instruction further including an address field of a predetermined bit length which identifies a test register holding a plurality of test bits greater than said predetermined bit length, the computer program product being loadable into a computer system and cooperating with the computer system to cause the test register identified in the address field to be accessed, a test condition held in the test register to be checked against at least one condition code, and the operation to be selectively carried out in dependence on whether the condition code satisfies the test condition.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings.